How to Achieve Impedance Matching in High-Speed PCB Routing Design

December 20, 2025

In high-speed circuit board routing, impedance matching is a core method to ensure signal integrity. Its purpose is to make the impedance of the signal source, transmission line, and load consistent to avoid signal reflection. The specific implementation needs to be carried out step by step, combining design goals, signal types, and material characteristics.

I.Define Target Impedance Values

First, determine the target impedance based on signal type and industry standards:

Single-ended signals: Commonly 50Ω (e.g., RF, high-speed serial signals), 60Ω/75Ω (for specific interfaces). Tolerance needs to be controlled within ±10%.
Differential signals: Commonly 100Ω (e.g., PCIe, USB 3.0, Ethernet), 90Ω (SATA). Tolerance ≤ ±10%.
Special scenarios: For example, DDR memory address lines might use 60Ω. Refer explicitly to the chip datasheet requirements.

II.Calculate Impedance via Stack-up and Parameters

Impedance is determined by the physical parameters of the transmission line and the PCB material characteristics, and must be calculated using formulas or tools.

1.Core Parameters:
Trace Width (W): Width of the signal trace.
Trace Thickness (T): Copper thickness (e.g., 1oz = 35μm, 2oz = 70μm).
Dielectric Thickness (H): Distance between the signal layer and the reference layer (ground/power plane).
Dielectric Constant (Er): The dielectric constant of the board material (e.g., FR-4 high-frequency version Er=3.8-4.2, Rogers material Er=3.0-3.5).

2.Calculation Tools:
Professional Software: Impedance calculators in Allegro, PADS, or third-party tools (e.g., Polar Si8000).
Formula Reference (Microstrip, Single-ended Impedance):
Z_0 = (87 / sqrt(Er + 1.41)) * ln( (5.98 * H) / (0.8 * W + T) )
(Specific formulas need adjustment based on transmission line type—microstrip, stripline, coplanar waveguide.)

3.Key Principle:
Impedance is inversely proportional to trace width (wider trace = lower impedance) and directly proportional to dielectric thickness (larger spacing = higher impedance). Adjust W and H to match the target value.

III.Impedance Control During Routing

1.Maintain Parameter Consistency: For the same signal group (e.g., differential pairs, clocks of the same frequency), trace width, spacing, and distance to the reference layer must be strictly consistent to avoid impedance discontinuities. Avoid sudden widening/narrowing of traces mid-route (e.g., jumping from 0.15mm to 0.2mm). If adjustment is needed, use a gradual taper (length ≥ 5 times the width difference).

2.Via and Connector Handling: Vias introduce parasitic capacitance and inductance, causing impedance discontinuities. Optimize via dimensions (e.g., hole diameter 0.3mm, pad diameter 0.6mm) and add ground vias nearby to shorten the return path. Reserve an impedance matching area at connector pins to ensure a smooth impedance transition from the transmission line to the pin (can be verified by simulation).

3.Disruptive Structures:
Route traces away from board edges and power/ground plane split lines to prevent impedance shifts due to edge effects.
For differential pair routing, maintain stable spacing (S) (typically S = 2-3 times the trace width W). Avoid crossing, branching, or changing spacing mid-route to ensure consistent differential impedance.

IV.Termination Matching Techniques (For Reflection Risk Points)

When the transmission line length exceeds 1/10 of the signal wavelength (common in high-speed signals), matching components need to be added at the source or termination to counteract reflections.

1.Source Termination:
Add a series resistor (R) at the signal source output so that R + R_source = Z_0 (e.g., source impedance 25Ω, series 25Ω resistor to match a 50Ω transmission line).
Suitable for clocks, high-speed control signals to reduce source-end reflections.

2.End Termination:
Parallel Termination: Place a resistor in parallel with the load to ground or power, making the load impedance equal to the transmission line impedance (e.g., 50Ω transmission line with a 50Ω resistor to ground).
Thevenin Termination: Use two resistors as a voltage divider (e.g., 33Ω + 18Ω = 50Ω), balancing impedance matching and DC level. Suitable for CMOS/TTL signals.
AC Termination: Series capacitor + resistor to avoid DC power consumption. Suitable for high-speed serial signals (e.g., PCIe).

3.Differential Termination:
Place a resistor across the termination of the differential pair (e.g., 100Ω) to match the differential impedance and absorb common-mode noise (common in high-speed differential interfaces).

V.Simulation and Verification

1.Design Phase: Use SI (Signal Integrity) simulation tools (e.g., HyperLynx, ADS) to model impedance profiles and check for discontinuity points (e.g., at vias, corners, connectors).

2.Production Phase: Request impedance test reports (TDR testing) from the PCB manufacturer to verify that the impedance of the produced transmission lines is within the tolerance range.

3.Debugging Phase: Measure signal eye diagrams with an oscilloscope. If the eye is closed or has significant jitter, it may be due to impedance mismatch, requiring adjustment of matching resistors or routing parameters.

The core of impedance matching is "consistency": From stack-up parameter calculation to routing detail control, and finally to termination component compensation, it is necessary to ensure the transmission line impedance matches the target value throughout the entire process. For high-speed signals (≥1 Gbps), simulation and verification are indispensable and can significantly reduce later-stage debugging costs.